1. Field of the Invention
The present invention generally relates to a reference voltage generating circuit and a constant voltage circuit using the reference voltage generating circuit, and particularly relates to a reference voltage generating circuit utilizing a difference in the work functions of gate electrodes between two field-effect transistors and to a constant voltage circuit using such reference voltage generating circuit.
2. Description of the Related Art
As shown in FIG. 19, a reference voltage generating circuit is conventionally known (see Patent Document 1) in which a depletion-type field-effect transistor and an enhancement-type field-effect transistor are connected in series, with a difference in the threshold voltages Vth of these field-effect transistors being extracted as a reference voltage Vref.
In FIG. 19, a transistor 105 is a depletion-type n-channel field-effect transistor, and a transistor 107 is an enhancement-type n-channel field-effect transistor. The drain current id of a field-effect transistor in the saturated state is represented as follows.id=(K)(Vgs−Vth)2  (a)In the equation (a), K represents a conductivity coefficient, and Vgs represents a voltage between the gate and the source.
Since the same current runs through the transistors 105 and 107, a voltage Vgs7 at a node 108 is represented as follows.Vgs7=Vth7−(K5/K7)1/2(Vth5)  (b)In the equation (b), K5 represents the conductivity coefficient of the transistor 105, K7 the conductivity coefficient of the transistor 107, Vth5 the threshold voltage of the transistor 105, and Vth7 the threshold voltage of the transistor 107.
When the conductivity coefficient K5 is set equal to K7, the equation (b) is expressed as follows.Vgs7=Vth7−Vth5  (c)
In this manner, the voltage Vgs7 of the node 108 is set to a difference in the threshold voltages between the transistor 105 and the transistor 107. This voltage is denoted as a reference voltage Vref in FIG. 20.
As shown in FIG. 21, a reference voltage generating circuit is known (see Patent Document 2) in which a constant current is made to run through a transistor having an n-type gate and a transistor having a p-type gate, with a difference in the threshold voltages of these transistors being extracted as a reference voltage Vref.
In FIG. 21, a constant current Io is made to run through a transistor T1 having an n-type gate and a transistor T2 having a p-type gate that have almost identical conductivity coefficients K, so that the constant current Io is represented as follows.Io=(K)(V1−Vth1)2=(K)(V2−Vth2)2  (d)In the equation (d), V1 represents the voltage between the drain and source of the transistor T1, Vth1 the threshold voltage of the transistor T1, V2 the voltage between the drain and source of the transistor T2, and Vth2 the threshold voltage of the transistor T2.
From the equation (d), the following equation is derived.V2−V1=Vth2−Vth1
In this manner, a difference in the drain voltages between the transistor T1 and the transistor T2 is extracted so as to extract a difference in the threshold voltages between the transistor T1 and the transistor T2.
FIG. 22 is a drawing showing a circuit diagram for extracting a difference in drain voltages (see Patent Document 2, for example). In the circuit shown in FIG. 22, the compositions of the gate electrodes of transistors are changed to provide different threshold voltages for the transistors T1 and T2, rather than using two types of transistors, i.e., a depletion-type transistor and an enhancement-type transistor.
[Patent Document 1] Japanese Patent Publication No. 4-65546
[Patent Document 2] Japanese Patent Application Publication No. 54-132753
The circuit of FIG. 21 has at least three problems as follows.
First, since two types of transistors, i.e., a depletion-type transistor and an enhancement-type transistor, are used, the threshold voltages Vth of the transistors vary independently of each other due to process variation, resulting in the initial precision of the reference voltage Vref being poor. With the variations of the threshold voltages Vth of the transistors being denoted as ΔVth5 and ΔVth7 as shown in FIG. 23, a variation in the reference voltage Vref ranges from −(ΔVth5+ΔVth7) to (ΔVth5 +ΔVth7). If Vth5=−0.5 V, Vth7=0.5 V, and ΔVth5=ΔVth7=0.15 V, for example, the reference voltage Vref may vary from 0.7 V to 1.3 V (±30%). There is thus a problem in that the reference voltage Vref suffers large variation.
Second, since two types of transistors, i.e., a depletion-type transistor and an enhancement-type transistor, are used, the temperature characteristics of the potential difference of the transistor channel regions are not identical, resulting in the temperature characteristics being poor. In order to improve the temperature characteristics, a ratio S5 (=W/L) of a channel width W to a channel length L of the transistor 105 and a ratio S7 (=W/L) of a channel width W to a channel length L of the transistor 107 may be adjusted to change the ratio S5/S7. However, this can only achieve approximately 300 ppm/° C. in the best case. In this manner, there is a problem in that the temperature characteristics of the reference voltage Vref are large.
Third, the source-drain voltages Vds5 and Vds7 of the transistors 105 and 107 are represented as follows.Vds5=VCC−Vg7Vds7=Vg7When the power supply voltage VCC fluctuates, thus, the source-drain voltage Vds5 of the transistor 105 ends up fluctuating also, resulting in the reference voltage Vref fluctuating in response to the fluctuation of the power supply voltage VCC. As shown in FIG. 24, the curve representing the relationship between the gate-source voltage Vgs of the transistor 105 and the drain current id is displaced as the power supply voltage VCC increases, thereby giving rise to a problem in that the reference voltage Vref increases by ΔVref.
The circuit shown in FIG. 22 overcomes the first and second problems described above, but cannot obviate the third problem since a resistor is used as a constant current source.
Accordingly, there is a need for a reference voltage generating circuit and a constant voltage circuit using the reference voltage generating circuit in which variation in the reference voltage due to process variation, temperature variation, and power supply voltage variation is reduced.